Article comprising a balanced driver circuit with less power dissipation than conventional circuit

ABSTRACT

By on-chip modification of a conventional balanced driver to yield special voltage levels, the power dissipation of a balanced, terminated transmission line circuit can be reduced by 50% or more relative to a conventional balanced driver or 25% or more relative to a conventional unbalanced driver. This reduction in power dissipation not only applies to point-to-point interconnections but also applies to bused interconnections. The low power balanced driver circuit can be implemented using ECL, BiCMOS, GaAs and CMOS technologies and no modifications are needed to the associated differential line receiver. Thus, the significant benefits of balanced interconnections, namely reduced crosstalk, increased noise immunity, and elimination of ground noise can be realized with a significant reduction in power dissipation.

FIELD OF THE INVENTION

This invention relates to integrated circuits and more specifically tobalanced driver circuits.

BACKGROUND OF THE INVENTION

A major performance limitation of electrical interconnections isinductive noise encountered when one interconnects high-speed, highpin-out integrated circuit (IC) chips having many drivers that switchsimultaneously. When a large number of drivers are activesimultaneously, a substantial transient current passes through theinductance of the ground and power distribution systems, causing a noisespike to emerge on the power and ground lines. The resulting fluctuationof the power and ground voltage levels can cause false switching ofdevices with an accompanying error or loss of data. As "Fast interfacesfor DRAMs," IEEE Spectrum, October 1992, pp. 52-57, shows, there existsa recognized need for improved interfaces between, e.g., DRAMs andprocessors, especially low cost interfaces that can have low powerdissipation.

Various techniques for reducing inductive switching noise on groundleads are known. They include the use of balanced IC driver circuits.However, conventional balanced IC driver circuits typically dissipatetwice the power of corresponding unbalanced drivers. This clearly is asignificant disadvantage. As can be seen from "Fast Interfaces forDRAMs" and problems experienced in the field, there is a long felt needfor a technique which will drive a circuit, produce a minimal amount ofinductive noise and dissipates a minimal amount of power.

Recently, a balanced driver circuit with reduced power dissipation wasdisclosed in U.S. patent application Ser. No. 07/895767 entitled"Balanced Driver Circuit For Eliminating Inductive Noise" filed on Jun.9, 1992, which is incorporated herein by reference. The circuit of the'767 application can reduce the power dissipation of a balanced driverto the level of that of an unbalanced driver, but has the drawback ofrequiring additional off-chip components. It would be highly desirableto have available a balanced driver circuit that can have still lowerpower dissipation, preferably without requiring additional components.This application discloses such a circuit.

SUMMARY OF THE INVENTION

This invention is embodied in an article that comprises a low powerbalanced driver circuit which essentially eliminates inductive noisewhile at the same time significantly reduces the power dissipationrelative to conventional balanced or unbalanced driver circuits. Theinventive balanced driver circuit, using ECL (emitter coupled logic), orBiCMOS (bipolar complementary metal-oxide semiconductor) technology,typically comprises two emitter follower output stages connected inseries to a pair of signal leads, respectively. Terminating the signalleads are two termination resistors. A voltage supply having a voltagedesignated by -V_(T) is connected between the termination resistors anda receiver is connected in parallel with the termination resistors.Surprisingly, it was discovered that there exist ranges of the relevantcircuit parameters (including V_(T) voltage levels, V₁ and V₂), whichcan result in substantially reduced power dissipation while avoiding ICperformance degradations. For the first time, one can utilize a lowpower balanced driver circuit not only to reduce inductive noise but toreduce power dissipation relative to a comparable unbalanced or balanceddriver circuit. In general, V_(T) is in the approximate range of 1.0 to1.5 V and the voltage swing, ΔV, is in the approximate range of 0.125 to0.375 V. The value of V₁ is realized by applying V_(T) approximately inthe range of 1.0 to 1.5 V, rather than the normal 2.0 V, between thetermination resistors. The value of V₂ =V₁ +ΔV is realized by changingthe value of internal resistors and/or changing the magnitude ofinternal current and/or voltage sources. This design can also beimplemented in CMOS (complementary metal oxide semiconductor) or GaAstechnologies. The driver can be used for driving point-to-pointinterconnections as well as bused interconnections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional unbalanced transmission line driver;

FIG. 2 illustrates a conventional balanced transmission line driver;

FIG. 3 illustrates a low power balanced transmission line driveraccording to the invention that uses ECL or equivalent CMOS logic forthe on-chip driver circuitry;

FIG. 4 illustrates a comparison of the total power dissipation of thelow power balanced driver with comparable, conventional balanced andunbalanced drivers;

FIG. 5 illustrates the total power dissipation of the low power balanceddriver.

DETAILED DESCRIPTION

Referring to the drawings, FIG. 1 schematically illustrates the outputportion of a conventional driver used to drive a terminated, unbalancedtransmission line. Only the AC portion of the unbalanced driver circuit1 is displayed. The unbalanced driver circuit 1 is comprised of anemitter follower output stage 4, positioned on an integrated circuit 2,a transmission line 6 which has an impedance designated by Z_(O), atermination resistor 10 which has a value designated by R_(T), typicallyequal to 50 Ω, and a voltage supply 8 which has a voltage designated by-V_(T), typically equal to -2 V. The average on-chip power dissipated bythe unbalanced driver circuit 1 less the power dissipated by the outputemitter follower 4 is denoted by P_(o). The typical ECL voltage swingfor an unbalanced driver circuit 1 is, ΔV=0.750 V, where the voltagelevels are approximately V₁ =-0.955 V, and V₂ =-1.705 V.

The total average power dissipation, P_(Ut), attributed to theunbalanced driver 1 is given by

    P.sub.Ut =P.sub.U +P.sub.o,                                (1)

where P_(U) denotes the average power dissipation of the output emitterfollower 4 and the termination resistor 10 as given by ##EQU1## P_(Ut)as a function of P_(o), is plotted in FIG. 4.

FIG. 2 schematically, illustrates the conventional method used to drivea terminated, balanced transmission line. Only the AC portion of thebalanced driver circuit 30 is displayed. The balanced driver 30 iscomprised of two emitter follower output stages 32 and 34 which are eachconnected in series to either a primary or secondary signal lead 36 and38 which together is referred to as a balanced transmission line havinga balanced impedance designated by Z_(B). Terminating the balancedtransmission line 36 and 38 are termination resistors 40 and 42 whichhave values designated as R_(T) typically equal to 50 Ω. A voltagesupply 44 which has a voltage designated by -V_(T), typically equal to-2 V, is connected to the center-tap of the termination resistors 40 and42. A receiver 46 is connected in parallel with the terminationresistors 40 and 42. The pair of signal leads 36 and 38 are connected tothe emitter follower output stages 32 and 34, respectively, located onthe integrated circuit 28 so that the current traversing the secondarylead 38 has the same amplitude, but the opposite sign as the currenttraversing the primary lead 36. Thus, there is negligible current returnthrough the common ground leads 48. The voltage swing and voltage levelsat the output of the emitter followers 32 and 34 of the conventionalbalanced driver circuit 30 are typically equal to the correspondingvoltage swing and voltage levels of the conventional unbalanced drivercircuit; e.g. ΔV=0.750 V, -V₁ =-0.955 V and -V₂ =-1.705 V. The averageon-chip power dissipated by the balanced driver circuit 30 less thepower dissipated by the two output emitter followers 32 and 34 alsoequals P_(o). Because a balanced driver circuit is essentially comprisedof two unbalanced driver circuits, the total average power dissipation,P_(Bt), attributed to the conventional balanced driver is given by

    P.sub.Bt =2P.sub.U +P.sub.o.                               (3)

Equation (3) is plotted in FIG. 4 and shows that for P_(o) =24 mW,P_(Bt) =77.6 mW, P_(Ut) =50.8 mW, the power of an unbalanced drivercircuit. Although the drivers 1 and 30 are represented here in ECLtechnology, equivalent CMOS technology with ECL voltage levels, GaAs,and BiCMOS technologies can also be used to drive terminatedtransmission lines.

The instant invention reduces the power dissipated by a balanced driver30, by on-chip modifications which modify the voltage swing, ΔV, andvoltage levels, V₁ and V₂, of the balanced driver circuit for a specialrange of values for V_(T). For the first time a low power balanceddriver circuit 50 can be applied to reduce the amount of inductive noiseand conserve power dissipation relative to a comparable unbalanced orbalanced driver circuit, while maintaining the minimum collector-currentof the emitter followers 52 and 54 above 1 mA. The typical configurationof the inventive low power balanced transmission driver 50 using ECL orBiCMOS technology is presented in FIG. 3. The low power balanced driver50 is comprised of two emitter follower output stages 52 and 54 whichare each connected in series to either a primary or secondary signallead 56 and 58 which together is referred to as a balanced transmissionline having a balanced impedance designated by Z_(B). Terminating thebalanced transmission line 56 and 58 are termination resistors 60 and 62which have values designated as R_(T), typically equal to 50 Ω. Avoltage supply 64 which has a voltage designated by -V_(T),approximately in the range of -1.0 to -1.5 V, is connected to thecenter-tap of the termination resistors 60 and 62. A receiver 66 isconnected in parallel with the termination resistors 60 and 62. The pairof signal leads 56 and 58 are connected to the emitter follower outputstages 52 and 54, respectively, located on the integrated circuit 68 sothat the current traversing the secondary lead 58 has the sameamplitude, but the opposite sign as the current traversing the primarylead 56. Surprisingly, it was discovered that when the voltage swing,ΔV, is in the approximate range of 0.125 to 0.375 V, the voltage supply64, -V_(T), is in the approximate range of -1.0 to -1.5 V, andappropriate on-chip modifications on the integrated circuit 68 weremade, voltage levels V₁, V₂ and voltage difference, δ=V_(T) -V₂,resulted which, in turn, resulted in significant reduction in powerdissipation relative to prior art driver circuits. Additionally, itshould be noted that with those modifications and reduction in powerdissipation no modifications to the conventional differential linereceiver 66 were needed.

Exemplarily, when balanced and unbalanced circuits occupy the samecircuit pack and are not segregated during the routing process of thecircuit pack, values for V_(T) and ΔV are such that V_(T) isapproximately in the range of 1.3 to 1.5 V and ΔV is approximately equalto 0.375 V, power dissipation is approximately in the range of 13 to 26mW as illustrated in FIG. 5. For V_(T) >1.5 V, the power dissipationbecomes greater than 26.8 mW, the total power dissipation of theconventional unbalanced driver circuit or the balanced driver circuit ofthe '767 application. For example, when V_(T) is equal to 2 V, the powerdissipation increases substantially to 68.6 mW as seen in FIG. 5. ForV_(T) <1.3 V, the value of the minimum collector current, Ic=δ/R_(T),becomes too close to cutoff and begins to degrade the performance of thecircuit. The voltage swing, ΔV, is desirably equal to 0.375 V so thatthe voltage swing, 2ΔV=0.750 V, propagated on the low power balanceddriver circuit (FIG. 3) is equal to the typical ECL voltage swingpropagated on the unbalanced driver circuit (FIG. 1). This is importantfor cross talk purposes when both balanced and unbalanced circuitsoccupy the same circuit pack. By applying V_(T), approximately equal to1.3 to 1.5 V, to the center-tap of the termination resistors 60 and 62,V₁ is automatically realized and knowing V₁ enables the determination ofV₂ =V₁ +ΔV. The appropriate value of V₂ is achieved through on-chipmodifications to the internal circuitry of the integrated chip 68,exemplary as discussed below.

Further reductions in power dissipation are obtained by reducing thebalanced signal swing below 2ΔV=0.75 V. This is especially importantwhen the unbalanced and balanced interconnections are segregated duringthe routing of the circuit pack. FIG. 5 shows the reduction of powerdissipation when ΔV is in the approximate range of 0.125 to 0.375 V.Again, the minimum collector current, I_(c), is above 1 mA.

The appropriate values for V_(T), ΔV, V₁ and V₂ were determined inrelation to the power dissipated by an unbalanced driver circuit. I havefound that the total average power dissipation, P'_(Bt), attributed tothe low power balanced driver 50 is given by

    P'.sub.Bt =2P.sub.U |.sub.V.sbsb.T,δ +P.sub.o(4)

where ##EQU2## From equation (5), it is seen that, for a given R_(T) andΔV, it is advantageous to reduce both V_(T) and δ as much as possible,consistent with the requirement that an acceptable collector currentlevel is maintained.

For ECL technology it was established by experiment that exemplarysuitable values for ΔV, V_(T), V₁ are 0.375 V, 1.3 V and 0.863 Vrespectively. Thus, V₂ =V₁ +ΔV=1.238 V, and δ=V_(T) -V₂ =0.062 V. Thevalue of V₁ is realized by applying V_(T) =1.3 V rather than the normal2.0 V as for the conventional unbalanced and balanced drivers 1 and 30in FIGS. 1 and 2. This is a result of the basic diode behavior of thecollector to emitter junction when in state V₁. The value of V₂ =1.238 Vis realized, with ECL drivers, by on-chip modifications which involvechanging the value of internal resistors and/or changing the magnitudeof the internal current source associated with the basic ECL driver. Seei.e. F100K ECL Logic Databook & Design Guide, by National Semiconductor,1990 Edition, Section 7, Chapter 1, which is incorporated herein byreference. Analogous on-chip modifications also apply to BiCMOS, GaAs,and CMOS drivers. By using the above special values of V_(T) and δ inequation (4), the total average power dissipation, P'_(Bt), can becomputed and is presented in FIG. 4 along with P_(Ut) and P_(Bt). Somespecial cases of these quantities when P_(o) =24 mW are also presentedin Table 1.

                                      TABLE 1                                     __________________________________________________________________________    Point-to-Point Interconnections                                               (.sup.--  P.sub.o = 24 mW, R.sub.T = 50 ohms)                                 Driver Type  Total Power Dissipation                                                                     V.sub.T                                                                           V.sub.2                                                                            V.sub.1                                                                            δ                                                                            ΔV                        __________________________________________________________________________    Conv Bal (FIG. 2)                                                                          .sup.--  P.sub.Bt = 53.6 + .sup.--  P.sub.o = 77.6                                          2.0 V                                                                             1.705 V                                                                            0.955 V                                                                            0.295 V                                                                            0.750 V                         Conv Unbal (FIG. 1)                                                                        .sup.--  P.sub.Ut = 26.8 + .sup.--  P.sub.o                                                 2.00.8                                                                            1.705                                                                              0.955                                                                              0.295                                                                              0.750                           Low Power Bal (FIG. 3)                                                                     .sup.--  P'.sub.Bt = 13.0 + .sup.--  P.sub.o                                                1.37.0                                                                            1.238                                                                              0.863                                                                              0.062                                                                              0.375                           __________________________________________________________________________

Thus, remarkably, the low power balanced driver 50 dissipates about 50%less power than the conventional balanced driver 30 and about 25% lesspower than the conventional unbalanced driver 1.

A similar method can be applied to determine the values V_(T), V₂, V₁,and δ when temperature, voltage, material, and manufacturing variationsare considered. Again, one begins by choosing a suitable value for ΔV,in the approximate range of 0.125 to 0.375 V, V_(T), in the approximaterange of 1.0 to 1.5 V, and V₁. Then one can determine V₂ =V₁ +ΔV, andδ=V_(T) -V₂. Finally, the average power dissipation can be computedusing equations 4 and 5.

The benefit of significantly reducing the power dissipation by a drivercan also be readily seen in bused interconnections. For busedinterconnections, any one active driver can send a digital bit stream tomultiple receivers. The bus may be unbalanced or balanced. To accomplishthis broadcast feature, the drivers are normally provided with a controlsignal which then allows each driver to have three states: V₁, V₂, andan off state (i.e. no electrical load on the bus). In operation, onlyone driver is active and the others are in the "off" state. The activebus driver must drive a load impedance that is one-half the loadimpedance of the corresponding point-to-point interconnections shown inFIGS. 1, 2 and 3. This additional load typically results in a doublingof the power dissipation in the emitter followers and the loadresistors. Thus, the benefit of using low power balanced driver circuits50 to drive bused interconnections is even greater.

I claim:
 1. An article comprising a circuit for driving electricalsignal output leads of an integrated circuit comprising:first and secondtransistor output stages each having an output terminal; first andsecond transmission lines, serially connected to said first and secondoutput terminals, respectively, each of said transmission lines havingan output end; first and second termination resistors connected seriallybetween said first and second transmission line output ends; a voltagesupply having a voltage V_(T) approximately in the range of 1.0 to 1.5volts connected between said first and second termination resistors; anda receiver connected between said first and second transmission lineoutput ends; wherein the circuit has a voltage swing, ΔV=V₂ -V₁,approximately in the range of 0.125 to 0.375 V, and voltage levels, V₁,V₂ which result in a significant reduction in power dissipated by thecircuit compared to analogous conventional balanced or unbalanced drivercircuits.
 2. An article according to claim 1 wherein the value of V₁ isrealized by applying said voltage, V_(T), to said circuit.
 3. An articleaccording to claim 1 wherein the value of V₂ is realized by the value ofresistors internal to the integrated circuit.
 4. An article according toclaim 1 wherein the value of V₂ is realized by the magnitude of currentsources internal to the integrated circuit.
 5. An article according toclaim 1 wherein the value of V₂ is realized by the magnitude of currentsources and resistors internal to the integrated circuit.
 6. An articleaccording to claim 1 wherein said integrated circuit is implementedusing emitter coupled logic.
 7. An article according to claim 1 whereinsaid integrated circuit is implemented using bipolar complementarymetaloxide semiconductor logic.
 8. An article according to claim 1wherein said integrated circuit is implemented using GaAs logic.
 9. Anarticle according to claim 1 wherein said integrated circuit isimplemented using complementary metal oxide semiconductor logic.
 10. Amethod of driving electrical signal output transmission lines of anintegrated circuit which reduces the inductive noise, and dissipatessubstantially less power than a corresponding conventional balanced orunbalanced driver circuit, the method comprising the steps oftransmitting a compensating signal on a secondary transmission lineassociated with each of said signal output transmission lines, applyinga voltage, V_(T), wherein V_(T) is approximately equal to 1.0 to 1.5 Vbetween a first and second terminating resistor serially connectedbetween said secondary and its associated transmission lines, providingvoltages V₁ and V₂, with ΔV=V₁ -V₂ being in the approximate range of0.125 to 0.375 V.